1. Field of the Invention
The present invention relates to a method for evaluating a semiconductor device having semiconductor elements comprised of an insulating film and an electrode on a semiconductor substrate, in more detail, to a method for evaluating a semiconductor device, by which dielectric breakdown of the insulating film can be rapidly evaluated with high precision. In addition, the present invention relates to a method for manufacturing a semiconductor device using the above evaluation method.
2. Discussion of the Background
As LSIs with Metal-Insulator-Semiconductor (MIS) structures have undergone a high level of integration in recent years, the reliability required of the insulating film has increased. The Time Zero Dielectric Breakdown (TZDB) method, Time Dependence Dielectric Breakdown (TDDB) method, and the like have been widely employed as methods of evaluating the reliability of the insulating film. The TDDB method is also employed to evaluate the lifetime of insulating films.
A common method of evaluating the reliability of insulating (oxide) films will be described below.
An oxide film is grown on a semiconductor substrate. Polycrystal silicon doped with impurities or a metal film is deposited thereon, and photolithography and etching are used to form electrodes. By the above steps, multiple MIS capacitors are fabricated. These MIS capacitors can be employed to evaluate the lifetime of insulating films in the following manner. First, current is applied to each element and the voltage between the electrode and substrate of each element is monitored. Here, if dielectric breakdown of the oxide film occurs, the absolute value of the applied voltage decreases suddenly. Thus, the lifetime of the insulating film can be evaluated based on the decrease in voltage.
Since the above dielectric breakdown is a statistical phenomenon, multiple elements must be measured to obtain reliable data. Further, multiple elements on a wafer must be evaluated to evaluate the quality of a wafer as a whole. However, when evaluating the quality of multiple elements, the evaluation of elements one by one is impractical because a great deal of time is required for measurement. Accordingly, measurement has been proposed in which plural elements are simultaneously measured.
For example, Japanese Unexamined Patent Publication (KOKAI) No. 2001-127126 (“Reference 1” hereinafter), which is expressly incorporated herein by reference in its entirely, discloses the application of constant-voltage stress to multiple elements employing a single power source to simultaneously measure multiple elements at the wafer level in a constant-voltage stress TDDB test.
The simultaneous evaluation of multiple elements at the wafer level by a constant-current stress method in which a certain stress is applied to insulating films in a test has also been proposed. For example, Japanese Unexamined Patent Publication (KOKAI) Heisei No. 5-335396 (“Reference 2” hereinafter), which is expressly incorporated herein by reference in its entirely, discloses a method of employing a single power source and connecting elements in series. Further, T. Hori, Gate Dielectrics and MOS ULSI, Spriger, p. 178 (“Reference 3” hereinafter), which is expressly incorporated herein by reference in its entirely, discloses a method of preparing multiple probes and probing multiple sample elements at once using a device in which each probe is equipped with a power source and ammeter.
However, in the method described in Reference 1, the effects of charges trapped at boundary levels and the like cause the voltage stress applied to the insulating film to fluctuate, creating a problem in the form of poor reliability.
In the method described in Reference 2, since a voltage of 10 volts or greater must be applied to each element, a voltage of several hundred volts is required when only about 10 samples are connected, for example, and the application of stress for extended periods is undesirable from the perspective of environmental safety. Further, in this method, limitations on the power source make it difficult to increase the number of elements being measured.
In the method described in Reference 3, when the density of the current flowing through the entire measurement system increases, the drops in voltage, in particular, due to parasitic resistance of the wafer stage and wafer substrate cannot be ignored. Further, for large wafers of 300 mm or more in diameter, for example, it is geometrically difficult to simultaneously bring all the evaluation elements on the entire wafer surface into contact without multiple probe needles numbering in the several hundreds or several thousands touching each other, and thus difficult to probe the entire wafer surface. The stress to which the wafer is subjected by each probe is about 20 to 50 g. If 1,000 points are simultaneously probed, the wafer is subjected to a stress of 20 to 50 kg. Thus, the wafer and the measurement device may sometimes be negatively affected. When the total surface of the wafer is divided up and probed in multiple measurements, the number of elements evaluated during a single measurement is lower when probing the peripheral portion of the wafer than when probing near the center of the wafer, due to unformed tips and the like. Thus, a smaller current flows through the entire system when evaluating the peripheral portion of the wafer. Since the potential of the substrate varies based on the probing site due to this difference in current, the amount of drop in voltage when dielectric breakdown occurs varies over the surface of the wafer. Normally, the voltage is monitored and dielectric breakdown is detected when the change in voltage exceeds a certain level. Thus, when the level of change in voltage varies over the wafer surface, it becomes difficult to accurately detect dielectric breakdown.